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Low power ADC 37.5 MS/s 12b

This IP describes a general purpose Analog to Digital Converter (ADC) for low-power applications. The converter is a charge-redistribution successive-approximation type converter, and it is suitable to operate in a time-interleaved ADC to enable higher sample-rates. As an example, this ADC is applied in a 2.5 GS/s ADC system. The key feature of this ADC is its low power consumption. Next to this, the full-scale range is programmable and its area is small. The IP product described in the datasheet is silicon proven. The 2.5 GS/s ADC system in which this ADC is applied fulfills all mass-production consumer electronics requirements.

The functional block diagram of the 37.5MS/s ADC is shown below.


  • sample-rate up to 37.5 MS/s
  • scalable full-scale input range 0.4-0.6 VPP,SE
  • low power consumption 6.3 mW
  • differential mode
  • 62 dB SNR
  • 70 dB SFDR (incl THD)
  • 12 bits, 10 ENOB
  • 0.03 mm2 in baseline 40 nm CMOS


  • Multi-mode digital receivers
  • Cable modems
  • Video digitizing and digital imaging
  • Portable instrumentation
  • Medical imaging

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