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Low latency SD ADC, 100dB DR

The LLSDADC100dB is a low power variant of our high-resolution sigma-delta analog-to-digital converter family. It achieves a dynamic range of more than 100 dB, at a power consumption of only 1.6 mW.

The latency of the ADC is only one clock cycle (40 ns at 25 MHz), which makes the converter ideally suited for application in control loops. The low latency is enabled by feeding the bitstream output back to the input via a DAC with build-in filtering. This creates a “tracking ADC behavior”, where the output accurately tracks the input signal inside the signal bandwidth. Next to enabling low latency, the filtering DAC also makes the system robust towards jitter and other error sources typically associated with 1-bit converters.

The LLSDADC100dB can convert both single-ended and differential signals with high accuracy. Next to this it can convert signals with amplitudes and biasing levels well outside its own supply level, by using external resistors acting as level shifters.

More information is available in the datasheet. The functional block diagram is shown below.


  • High dynamic range: >100 dBA (20 Hz – 20 kHz)
  • Low power: 1.6 mW per ADC
  • Low Area: 0.3 mm2 per ADC
  • Low latency: only one clock period (40 ns)
  • Low noise reference without external components
  • Supports wide common mode range (true ground to supply & capacitive coupling)
  • Supports both differential and single-ended input
  • Supports 4 internal gain settings
  • Using external resistors allows:
    • Additional gain settings
    • Extended input voltage range, well outside supply voltage range
  • Silicon proven in 0.14 μm CMOS


  • High-quality audio ADC & DAC (codec)
  • Digital control loops (enabled by its low latency)
  • Sensor read-out
  • Instrumentation

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