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Xcelera-CL VX4

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The Xcelera-CL VX4 is the next generation user programmable vision processor based on the PCI Express X4 platform. It features powerful embedded processing architecture for real-time high-performance machine vision applications. The Xcelera-CL VX4 combines field-proven image acquisition with onboard processing capabilities.

The X64 Xcelera-CL VX4 Full is a Camera Link vision processor that is based on the PCI Express x4 interface. Compatible with a Base, Medium or Full Camera Link® camera, the X64 Xcelera-CL VX4 Full supports a wide variety of multi-tap area and line scan colour and monochrome cameras. The X64 Xcelera-CL VX4 Full board can interface with advanced Camera Link cameras output formats including 10-taps of 8-bit at 85MHz pixel clock rates.

Sophisticated Embedded Processing Platform

The Xcelera-CL VX4 Full features FPGA hardware processing platform that combines ACU(Acquisition Control Unit), DTE (Data Transfer Engine) and IPU(Image Processing Unit) and state of the memory architecture. As a result, Xcelera-CL VX4 is capable of handling variety of complex, real-time image processing topologies including iterative processing loops. While the FPGA technology provides ability to adapt to variety of high-speed, compute intensive real-time processing applications, the Xcelera-CL VX4 hardware design have been implemented using standard off-the-shelf components with long term availability. 
 

Develop, Deploy, and Debug Embedded Solutions with Real-Time Performance

The Xcelera VX4 vision processors features an FPGA hardware processing platform that combines ACU(Acquisition Control Unit), DTE (Data Transfer Engine) and IPU (Image Processing Unit) and state of the memory architecture, making it capable of handling variety of complex, real-time image processing topologies including iterative processing loops. While the FPGA technology provides ability to adapt to variety of high-speed, compute-intensive real-time processing applications, the hardware design has been implemented using standard off-the-shelf components with long term availability.

Key Features:

  • Highly optimized memory architecture for embedded image processing
  • Up to 2 x 512MB of Image memory
  • Up to 4 x 32MB of image processing memory
  • Extensive camera support
  • User configurable Xilinx Virtex 5 FPGA
  • Fully supported by Sapera APF

 

Hardware Architecture

 

Sapera APF

Sapera APF is an integrated graphical FPGA development environment. The Sapera APF simplifies traditional FPGA development processes by combining a point and click graphical interface with FPGA based image processing libraries. Sapera APF comes bundled with a bit accurate software version of the FPGA library functions for rapid functional simulation but also automatically generates necessary infrastructure to call user functions using Sapera SDK. This powerful, yet easy to use FPGA development environment allows users to create, debug, and deploy FPGA code without ever leaving the development GUI, dramatically improving ease of development and time to deployment.

Sapera APF Interface
  • Enables Real-time embedded image processing
  • Rapid design implementation using
  • Point & Click IDE
  • Software-centric approach
  • Extensive set of image processing functions for the FPGA
  • Bit-accurate software functions permit verification of algorithm behavior
  • Automatic software interface generation for user-created hardware designs
  • Seamless interface to Xilinx tools

 

 

Embedded Image Processing Libraries

Sapera APF includes over 150 imaging functions in FPGA-based embedded image processing libraries, as well as bit-accurate software version of the FPGA library functions for rapid functional simulation. Sapera APF automatically generates necessary infrastructure to call user functions using Sapera SDK.

Basic Operations   Advanced Operations
  • Arithmetic operations
  • Color Space Conversion
  • Logic operations
  • Bayer conversion
  • Pixel operations
  • Streams
  • Neighborhood operations
  • Memory access
  • Statistics
  • GPI/O control
  • Camera I/O control
  
  • Rotation by arbitrary angle
  • Loss-less compression
  • RLE
  • Image compression

Upcoming Functions (1)

  • Warping
  • Wavelet Encoding
  • Blob Analysis
  • JPEG Compression

(1) Contact Teledyne DALSA for details
FeatureSpecification
Part NumberXcelera-CL_VX4
Camera Interface1 Base, Med., or Full
Camera FormatBase, Med., Full Camera Link
Pixel Clockup to 85 MHz MHz
Bits/Pixelup to 16
Number of Camera Tapsup to 10-tap/8-bit or 8-tap/10-bit
Host BusPCIe x4
Frame Buffer2 x 512 MB
Advanced Features FPGA hardware processing platform
OS SupportXP Pro, Windows 7 (32/64-bit)
SoftwareSapera Vision Software
GPIOOn-board 4-in/4-out

Documents

Sapera APF Datasheet Sapera APF Datasheet
Xcelera-CL VX4 Datasheet Xcelera-CL VX4 Datasheet

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Feature Highlights

  • Half-length PCI Express x4 Board
  • Acquires images from one Base, Medium or Full Camera Link® camera
  • Real-time FPGA based hardware processing
  • User programmable FPGA tools
  • Supports Camera Link operations up to 85MHz
  • Extended feature set supports advanced Camera Link pixel/tap configurations
  • Windows® XP and Windows 7 (32/64-bit) compatible
  • Fully supported by Sapera Vision Software SDKs
  • FCC, CE and ROHS compliant
     

Compatible Teledyne DALSA Products

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