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TSVs: Through Silicon Vias

Enabling 3D MEMS Integration

TSVs are high performance interconnect techniques that are key enabling technologies for 3D integration of MEMS. Compared to 3D techniques such as flip chips, wire bonds, or package-on-package, the density of through-silicon vias is substantially higher, and the length of the connections is shorter. Teledyne DALSA is pleased to offer both silicon and copper TSVs. Each has its particular strength. Teledyne DALSA is pleased to offer both silicon and copper TSVs; our sister foundry Teledyne Micralyne offers polysilicon and metal TSVs. Each TSV type has its particular strength. 

TSVs are usually categorized as ‘Via-First’ or ‘Via-Last’, the main differentiator being that via-first take place before wafer bonding and are able to withstand temperatures of several hundred degrees. Via-last are post bonding, and typically the temperatures involved need to be low enough to prevent damage to back-end CMOS layers.

Copper filled 5µm wide trench before planarization

Key Features and Benefits

Silicon TSVs

  • Via-First TSV with silicon
  • Vias formed using bulk-silicon with oxide-filled trench isolation
  • Smaller vias can be made with electrically isolated doped poly
  • TSV is standard with Teledyne DALSA’s inertial sensor platform

Teledyne-DALSA Via–First TSVs can use the trench fill (in-situ doped poly) as the conductor, or if larger vias are required, the conductive region can be the MEMs wafer itself, in which case the trenches are used only to provide isolation. This technology is available for both 150mm and 200mm wafers. 

Copper TSVs

  • Via-Last technology with copper vias
  • Filled using low temperature electrochemical process.
  • 5um CD on thinned wafers – post-bonding
  • This process is available for 200mm wafers only

Teledyne DALSA’s Via-Last technology utilizes copper vias, filled using the aveni low temperature electrochemical process. This technology produces perfect filling of 100 µm deep vias only 5µm diameter, which connect to the outside world through a copper redistribution layer and Ni/Au UBM. 

Wafer Level Packaging (WLP)

Surface mountable 3D ICs use wafer level packaging for dramatic size and form factor reduction with corresponding cost reductions, making them ideal for mobile applications. Teledyne DALSA offers advanced I/O options including µBGA, solderable pads, or standard pads for stacked die and co-package designs, with hermetic seals for oscillators, pressure and image sensors, and non hermetic for RF filters, microfluidics and Si microphones.